Development of Secure Intersystem Communication Mechanisms inside of a Type-1 Hypervisor

Development of Secure Intersystem Communication Mechanisms inside of a Type-1 Hypervisor

The goal: to develop new techniques of efficient and secure utilization of shared resources in heterogeneous environment with multiple operating systems via usage of new intersystem communication mechanisms inside of a type-1 hypervisor.

[GSoC 2017 Results: RTEMS for HiFive1] The Final Report

Google Summer of Code 2017 Results

Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors

Student: Denis Obrezkov

Mentors: Joel Sherrill, Hesham Almatary

The Goal and Objectives

This project aimed to provide the RTEMS community with a new capability of utilizing the power of SiFive FE310 processors. Since the main goal of the project was to provide developers of embedded systems with new capabilities, a few objectives were defined:

• to implement HiFive1 BSP with a console and clock driver support
• to provide project documentation.

These well-defined objectives were achieved during Google Summer of Code 2017. In the following parts of the document it will be shown how to utilize the results of the work, what problems were overcome during the project and what constraints the current solution has. Also, some links to valuable patches, sources and blog posts with a description of the made work will be provided. Finally, there will be some notes about the future involvement.

[GSoC 2017 with RTEMS: Phase 2 Results] Now BSP can send messages and fails to tick

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during  the Phase 2 and what are the plans for the next Phase. 

[GSoC 2017 with RTEMS: Phase 2 Week 0] Working with interrupts on HiFive1

The purpose of this post is to show how interrupts in the HiFive1 board should be handled. I don't want here to describe a relation between RTEMS interrupt handling and  RISCV interrupt infrastructure. First of all, I want to describe FE310 SoC interrupt architecture and how interrupts can be initialized and handled on this architecture.

[GSoC 2017 with RTEMS: Phase 1 Last week] Summarizing Phase 1 results

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during this week, during the Phase 1 and what are the plans for the next week. Also, we will see how to compile RTEMS BSP for HiFive1 board in its current state.

[GSoC 2017 with RTEMS: Week #0] Building a simple binary for HiFive1 Board

The purpose of this article is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during this week and what are the plans for the next week.

[Week before GSoC 2017: RTEMS for HiFive1] Building toolchain, simulator and learning ISA

The purpose of this article is to show how to build RISCV simulator.