Saturday, 10 June 2017

[GSoC 2017 with RTEMS: Week #0] Building a simple binary for HiFive1 Board

The purpose of this article is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during this week and what are the plans for the next week.

Project information

Project name: Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors
Link to the project: link 
Project timeline: timeline
GitHub Link: GitHub

Current state

In the beginning of the last week I had several issues. For example, though I had a Hesham Almatery's RISC-V BSP of RTEMS for SPIKE platform - it didn't work. The reason for this was an outdated instruction set - Hesham's port was made two years ago and it used a privileged ISA v1.9 or earlier. Thus, I had such errors like 'unrecognized opcode eret'. Also, since 2015 RTEMS slightly changed it's structure so some files were missing from the build. This problem was solved by changing configuration files, and Hesham also changed his BSP to make it work with priv-1.10 ISA on SPIKE. Thus, now we had a RTEMS BSP for RISCV32 that can be built for SPIKE simulator: Hesham's repo.

Another problem I wanted to solve - to make program run on top of HiFive1 board. The main difficulty was to provide working start.S and linker file implementation. Somehow, my gdb didn't want to step through 'call boot_card' instruction - it just hung. There were several opinions - gdb doesn't want to make long jumps, gdb doesn't work with some addresses, I even thought that some manipulation with Debug registers should be done. But the solution was simple - gdb didn't want to work with RAM more than 16 KiB. And how to solve that is the issue for the current week. There is only 16 KiB of RAM, and I was confused with E31 Coreplex core, that allows up to 64 KiB of RAM, and I assumed that it has that amount. So, at the moment everyone can take the code from my repo HiFive1 branch, download RTEMS source builder, take patches from Hesham's repo and apply them, build RTEMS and step through the code with a debugger.

Plans for the next week

The plans are very simple:
  • to provide appropriate linker and start.S files
  • to start to develop Console Driver in polling mode
  • to discuss with Hesham interrupts handling
  • to figure out how to make gdb work with 64 KiB of RAM only 16 KiB is available.
That's all, see you next week!

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