[GSoC 2017 with RTEMS: Phase 1 Last week] Summarizing Phase 1 results

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during this week, during the Phase 1 and what are the plans for the next week. Also, we will see how to compile RTEMS BSP for HiFive1 board in its current state.

Project information

Project name: Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors

Link to the project: link 

Project timeline: timeline

GitHub Link: GitHub

Current state

The current state of the project - the board is now able to run small RTEMS programs.

Last three weeks I was trying to run my BSP on top of the HiFive1 board. I encountered several problems. First of all, RTEMS required too much space for its workspace - it wanted about 15 KiB, while HiFive1 has only 16 KiB. At the same time, there were other sections placed in RAM. This problem was partially solved by using a low ticker example which requires much less memory.

Another problem to solve was about strange values during execution. For example, though in source code it was stated that a variable should be '3', it had the value of a random number during execution. The problem was with uninitialized .data section. In the BSP, on which HiFive1 is based, there were no code for copying data values from ROM to RAM. After this code addition the problem disappeared. 
As for now small programs can be executed, but the BSP lacks several features:

• local and global interrupts handling
• clock and console drivers
• all the peripheral drivers (uart, spi, pwm).

Also, there are several bugs, for example, minimum rtems example executes with the error INTERNAL_ERROR_THREAD_EXITTED. Another problem is that at the time of this writing there is no support for many examples due to their size, or, for examples-v2, due to the wrong linker file (examples-v2 use their own linker file).

Plans for the Phase 2

During the next stage I want to implement all local interrupts handlers and a clock driver. If there will be time I also will implement a new linker file. In order to do this I will have to communicate a lot with my mentor, because this linker file should be implemented utilizing the new scheme: one common architecture linker file + file(s) for each BSP.