[GSoC 2017 with RTEMS: Phase 2 Results] Now BSP can send messages and fails to tick

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during  the Phase 2 and what are the plans for the next Phase. 

Project information

Project name: Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors

Link to the project: link 

Project timeline: timeline

GitHub Link: GitHub

Current state

The current state of the project - the board is now able to send messages via uart (console output is available). This means that oscillators are also works well, so it is possible now to set up a required frequency.
During last three weeks I was trying to set up SoC's frequency, to enable message sending through uart and to make the clock driver work. I was quite successful with first two tasks but the clock driver doesn't work properly in its current state. The possible issue is a mistake in context switch/restore routine.

Plans for the The Final Phase

During the next Phase (Final period) me and my mentors decided that it is better to try to implement the interrupt-driven clock driver. Thereby, during next stage I will have to:

• implement RTEMS interrupt handling scheme for HiFive1 BSP
• make the interrupt driven clock driver work
• make console work to full extent.

Since this will be the last phase I also will have to write a blog post describing my work, my results and possible future improvement.