Wednesday 18 October 2017

Development of Secure Intersystem Communication Mechanisms inside of a Type-1 Hypervisor

Development of Secure Intersystem Communication Mechanisms inside of a Type-1 Hypervisor


The goal: to develop new techniques of efficient and secure utilization of shared resources in heterogeneous environment with multiple operating systems via usage of new intersystem communication mechanisms inside of a type-1 hypervisor.

Sunday 27 August 2017

[GSoC 2017 Results: RTEMS for HiFive1] The Final Report

Google Summer of Code 2017 Results

Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors

Student: Denis Obrezkov
Mentors: Joel Sherrill, Hesham Almatary

The Goal and Objectives

This project aimed to provide the RTEMS community with a new capability of utilizing the power of SiFive FE310 processors. Since the main goal of the project was to provide developers of embedded systems with new capabilities, a few objectives were defined:
  • to implement HiFive1 BSP with a console and clock driver support
  • to provide project documentation.

These well-defined objectives were achieved during Google Summer of Code 2017. In the following parts of the document it will be shown how to utilize the results of the work, what problems were overcome during the project and what constraints the current solution has. Also, some links to valuable patches, sources and blog posts with a description of the made work will be provided. Finally, there will be some notes about the future involvement.

Monday 31 July 2017

[GSoC 2017 with RTEMS: Phase 2 Results] Now BSP can send messages and fails to tick

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors"Further you will see what was done during  the Phase 2 and what are the plans for the next Phase. 

Monday 3 July 2017

[GSoC 2017 with RTEMS: Phase 2 Week 0] Working with interrupts on HiFive1

The purpose of this post is to show how interrupts in the HiFive1 board should be handled. I don't want here to describe a relation between RTEMS interrupt handling and  RISCV interrupt infrastructure. First of all, I want to describe FE310 SoC interrupt architecture and how interrupts can be initialized and handled on this architecture.

Wednesday 28 June 2017

[GSoC 2017 with RTEMS: Phase 1 Last week] Summarizing Phase 1 results

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors"Further you will see what was done during this week, during the Phase 1 and what are the plans for the next week. Also, we will see how to compile RTEMS BSP for HiFive1 board in its current state.

Saturday 10 June 2017

[GSoC 2017 with RTEMS: Week #0] Building a simple binary for HiFive1 Board

The purpose of this article is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during this week and what are the plans for the next week.

Tuesday 23 May 2017

Investigation of possibility to create an open LLVM-based Ada compiler [rejected]

This is a closed project. The purpose of this post was to collect as much as possible information about LLVM, Ada compilers and possible people to contact and organizations who can provide some help.

Sunday 21 May 2017

[PreGSoC 2017] Make a port of RTEMS for HiFive1

The purpose of this post is to provide all available sources of information for everyone who is interested in my GSoC 2017 project "Utilizing full power from HiFive1 via usage of RTEMS on top of Freedom E310-G000 cores". Also, in this post other things will be described, such as the current state, available repositories and toolchains, plans for further involvement. 

Saturday 6 May 2017

First steps with stm32l152. SPI handling with LCD 5110 display.


One of the most interesting parts of embedded programming is a work with graphic displays. Some of them are easy to manage, others require special tricks. The objective of this post is to show how to use the simplest and famous display – Nokia 5110 LCD. Also, it will be demonstrated how to use SPI in an unidirectional master mode.

Tuesday 18 April 2017

First steps with stm32l152. Uart handling.

The purpose of this introductory post is to show how to receive data via Uart from a host machine. Also, I will see how to create a simple FreeRTOS task.

Sunday 12 February 2017

Building RTEMS and its example for sparc architecture

The purpose of this work is to show how to easily get started with RTEMS real-time operating system. In the article I will show how to compile RTEMS, compile 'Hello World' application and run it in a simulator. The example and RTEMS system itself will be compiled for sparc/erc32 architecture and will be launched in the simulator. More information about RTEMS you can find on the official site: rtems.org.

Friday 13 January 2017

First steps with stm32l152. UART and SPI simple program.

In this post I want to describe the simplest program, which transferring bytes from our board using UART and SPI interfaces.
First of all, we should setup our pins. I will do it in CubeMX, though if you want to deeper understand these interfaces, you can read through datasheets and set up them manually.


Wednesday 4 January 2017

First steps with stm32l152c-discovery. Moving to Qt Creator



In the last two posts I described an environment installation and the first project generation. I used Eclipse as IDE. I want to be honest, I don't like Eclipse. It's very slow and sometimes buggy. So, I decided to show how to move to Qt Creator.
In this post you need to download Qt Creator from its site: https://www.qt.io/ide/ or install it with your software manager, in debian:

apt-get install qtcreator.

But be aware, that repositories may contain not the last version of the IDE.