[GSoC 2017 with RTEMS: Phase 2 Results] Now BSP can send messages and fails to tick

The purpose of this article (as always with GSoC articles) is to review the current state of the GSoC Project: "Utilizing full power of RISC-V architecture via usage of RTEMS on top of SiFive FE310 processors". Further you will see what was done during  the Phase 2 and what are the plans for the next Phase. 

[GSoC 2017 with RTEMS: Phase 2 Week 0] Working with interrupts on HiFive1

The purpose of this post is to show how interrupts in the HiFive1 board should be handled. I don't want here to describe a relation between RTEMS interrupt handling and  RISCV interrupt infrastructure. First of all, I want to describe FE310 SoC interrupt architecture and how interrupts can be initialized and handled on this architecture.